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• Write Data Interleaving in AXI ~ Chip Guru

  Write data interleave happen when two AXI bus masters generate sequence of write data to the same slave, but the write data doesn't arrive e...

• WELCOME TO CHIP GURU ~ Chip Guru

  This is the Blog where we can discuss the tidbits of asic design, which will Help us to be a chip guru. Other Advantages of this blogs...

• Create a table of contents in Microsoft Word ~ Chip Guru

  The easiest way to create a table of contents is to use the built-in outline-level (outline level: Paragraph formatting you can use to assig...

• Multiply and Divide Tricks ~ Chip Guru

  // Binary Multiplication Algorithm // Simple Multiplication Hardware // Streamlined Multiplication Hardware // Booth Recoding for Higher-Rad...

• FIFO Depth Calculation . ~ Chip Guru

  FIFO ( First in First Out )  are essential part of any design, we use FIFOs for synchronizing two clock domains , For synchronizing we need ...

• String tasks in verilog ~ Chip Guru

  Note : If you are planning to use these Tasks with SystemVerilog then Please change byte to byte1 & char to char1 because both are keywords ...